Semiconductor device and a method of manufacturing the same

ABSTRACT

A semiconductor IC device which includes a circuit region and a peripheral region on a main surface of a semiconductor substrate, a first insulating film formed over the main surface, external terminals arranged in the peripheral region and formed over the first insulating film, a conductive guard ring formed over the first insulating film and provided around the external terminals, and second insulating films formed in the internal region and the peripheral region, the second insulating film in the peripheral region is formed over the first insulating film and over the guard ring and is contacting the external terminals, the second insulating films of the circuit region and that of the peripheral region are separately formed and are isolated from each other. Separate second insulating film may be formed over the wirings of one or more of existing wiring levels of the semiconductor device.

This application is a Divisional Application of U.S. application Ser.No. 11/602,196, filed Nov. 21, 2006, which, in turn, is a Continuationof U.S. application Ser. No. 10/732,518, filed Dec. 11, 2003, and nowU.S. Pat. No. 7,189,637; and the entire disclosures of which areincorporated herein by reference.

BACKGROUND OF THE INVENTION

This invention relates to a method of manufacturing a semiconductordevice. More particularly, the invention relates to an effectivetechnique for the formation of wiring in the manufacture ofsemiconductor devices.

The wiring structure of a semiconductor device includes wirings forpassing signals or an electric current, and an insulating film isprovided for insulating the wirings. It has been accepted that thewirings of a semiconductor device are provided for the purpose oflowering the resistance, and the insulating film is provided for thepurpose of achieving complete insulation.

The wiring structure of a semiconductor device is described, forexample, in Japanese Patent Application Laid-open No. Hei 8(1996)-204006, which discloses a technique for covering a wiring with anetch stopper film and a technique for arranging a wiring on an etchstopper film.

[Patent Document]

Japanese Patent Application Laid-open No. Hei 8 (1996)-204006.

SUMMARY OF THE INVENTION

In this connection, we have found for the first time that theabove-mentioned wiring techniques have the following problems.

When an electric charge built up in a wiring in the course of theprocess of manufacture of a semiconductor device exceeds a given level,a discharge takes place between adjacent wirings. As a result, high heatenergy is instantaneously generated between adjacent wirings to deformthe material of the wiring, with the attendant problem thatshort-circuiting takes place between adjacent wirings. Especially, thisproblem is apt to occur in a case where, as at least one objectivewiring, there is a long wiring that is likely to build up an electriccharge therein, or this problem can occur at a portion where wiringshaving a potential difference are arranged adjacent to each other.Moreover, as wirings become more highly integrated, the space betweenadjacent wirings becomes narrow, thereby causing the problem to becomemore pronounced.

An object of the present invention is to provide a technique forsuppressing or preventing a failure due to short-circuiting betweenwirings of a semiconductor device.

The above and other objects and novel features of the present inventionwill become apparent from the description provided in this specificationand from the accompanying drawings.

Among those features set out in the present application, a typicalfeature of the present invention can be briefly summarized as follows.The invention is contemplated to provide a wiring structure for asemiconductor device wherein an insulating film used therein has thefunction of permitting an electric charge that has accumulated in thewiring to escape.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view showing, in the course of a manufacturingprocess, a typical portion of a semiconductor device, illustrating aconventional problem found by us for the first time;

FIG. 2 is a sectional view showing an example of a typical portion of asemiconductor device according to one embodiment of the invention;

FIG. 3 is an enlarged, sectional view of region A of FIG. 2;

FIG. 4 is a graph showing the relation between current I and voltage Vof an ordinary silicon oxide film;

FIG. 5 is a graph showing the relation between current I and voltage Vof a silicon-rich silicon oxide film;

FIG. 6 is a graph showing the relation between current I and voltage Vof a silicon-rich silicon oxide film;

FIG. 7 is a graph showing the relation between current I and voltage Vof a silicon-rich silicon oxide film;

FIG. 8 is a graph showing the relation for comparison between therefractive index and the current of a silicon oxide film having athickness of approximately 30 nm;

FIG. 9 is a graph showing the relation between the thickness and thecurrent of a silicon-rich silicon oxide film having a refractive indexof 1.55;

FIG. 10 is a graph showing the relation between current I and voltage Vof a silicon oxynitride film;

FIG. 11 is a diagram showing an example of a cleaning device used in themanufacturing process of a semiconductor device according to theembodiment of the invention;

FIG. 12 is a sectional view of a typical portion of a wafer in thecourse of the process of manufacture of the semiconductor device ofFIGS. 2 and 3;

FIG. 13 is a sectional view of a typical portion in the course ofmanufacture of the semiconductor device subsequent to FIG. 12;

FIG. 14 is a sectional view of a typical portion in the course ofmanufacture of the semiconductor device subsequent to FIG. 13;

FIG. 15 is a sectional view of a typical portion in the course ofmanufacture of the semiconductor device subsequent to FIG. 14;

FIG. 16 is a sectional view of a typical portion in the course of themanufacture of the semiconductor device subsequent to FIG. 15;

FIG. 17 is a timing chart showing a film-forming sequence in theformation of an insulating film of the semiconductor device of FIGS. 2and 3;

FIG. 18 is a sectional view of a typical portion of a semiconductordevice according to another embodiment of the invention;

FIG. 19 is a sectional view of a typical portion of a wafer in thecourse of manufacture of the semiconductor device of FIG. 18;

FIG. 20 is a sectional view of a typical portion of the wafer in thecourse of manufacture of the semiconductor device subsequent to FIG. 19;

FIG. 21 is a sectional view of a typical portion of the wafer in thecourse of manufacture of the semiconductor device subsequent to FIG. 20;

FIG. 22 is a sectional view of a typical portion of the wafer in thecourse of manufacture of the semiconductor device subsequent to FIG. 21;

FIG. 23 is a sectional view of a typical portion of the wafer in thecourse of manufacture of the semiconductor device subsequent to FIG. 22;

FIG. 24 is a diagrammatic plan view of a typical portion of asemiconductor device according to a further embodiment of the invention;

FIG. 25 is a sectional view, taken along the line X1-X1 in FIG. 24;

FIG. 26 is a sectional view of a structure illustrating the defect whichwe have studied;

FIG. 27 is a sectional view of a typical portion of a semiconductordevice according to a still further embodiment of the invention;

FIG. 28 is a sectional view of a typical portion in the course ofmanufacture of a semiconductor device for illustrating the problemchecked by us;

FIG. 29 is a sectional view of a typical portion of a wafer in thecourse of manufacture of the semiconductor device subsequent to FIG. 28;

FIG. 30 is a sectional view of a typical portion of the wafer in thecourse of manufacture of the semiconductor device subsequent to FIG. 29;

FIG. 31 is a sectional view of a typical portion of a semiconductordevice according to another embodiment of the invention;

FIG. 32 is a sectional view of a typical portion of a semiconductordevice according to still another embodiment of the invention;

FIG. 33 is a sectional view of a typical portion in the course ofmanufacture of a semiconductor device for illustrating the problemchecked by us;

FIG. 34 is a sectional view of a typical portion of a semiconductordevice according to yet another embodiment of the invention;

FIG. 35 is a sectional view of a typical portion of a semiconductordevice according to a further embodiment of the invention;

FIG. 36 is a sectional view of a typical portion of a semiconductordevice according to another embodiment of the invention;

FIG. 37 is a sectional view of a typical portion showing the state wherecontact holes and plugs are provided at the semiconductor device of FIG.36;

FIG. 38 is a sectional view of a typical portion of a semiconductordevice according to another embodiment of the invention;

FIG. 39 is a sectional view of a typical portion at a face vertical tothe section of FIG. 38;

FIG. 40 is a sectional view of a typical portion of a semiconductordevice according to another embodiment of the invention;

FIG. 41 is a sectional view of a typical portion of a semiconductordevice according to still another embodiment of the invention;

FIG. 42 is an enlarged sectional view of the region G of FIG. 40;

FIG. 43 is a sectional view of a typical portion of a wafer in thecourse of manufacture of the semiconductor device of FIG. 41;

FIG. 44 is a sectional view of a typical portion of the wafer in thecourse of manufacture of the semiconductor device subsequent to FIG. 43;

FIG. 45 is a sectional view of a typical portion of the wafer in thecourse of manufacture of the semiconductor device subsequent to FIG. 44;

FIG. 46 is a sectional view of a typical portion of the wafer in thecourse of manufacture of the semiconductor device subsequent to FIG. 45;

FIG. 47 is a sectional view of a typical portion of the wafer in thecourse of manufacture of the semiconductor device subsequent to FIG. 46;

FIG. 48 is a sectional view of a typical portion of the wafer in thecourse of manufacture of the semiconductor device subsequent to FIG. 47;

FIG. 49 is a sectional view of a typical portion of the wafer in thecourse of manufacture of the semiconductor device subsequent to FIG. 48;

FIG. 50 is a sectional view of a typical portion of the wafer in thecourse of manufacture of the semiconductor device subsequent to FIG. 49;

FIG. 51 is a sectional view of a typical portion of a semiconductordevice according to another embodiment of the invention;

FIG. 52 is a sectional view of a typical portion of a wafer in thecourse of manufacture of the semiconductor device of FIG. 51;

FIG. 53 is a sectional view of a typical portion of the wafer in thesource of manufacture of the semiconductor device subsequent to FIG. 52;

FIG. 54 is a sectional view of a typical portion of the wafer in thecourse of manufacture of the semiconductor device subsequent to FIG. 53;

FIG. 55 is a sectional view of a typical portion of the wafer in thecourse of manufacture of the semiconductor device subsequent to FIG. 54;

FIG. 56 is a plan view of a semiconductor chip of a semiconductor deviceaccording to another embodiment of the invention;

FIG. 57 is an enlarged plan view of the region J of FIG. 56;

FIG. 58 is a sectional view taken along line X2-X2 in FIG. 57;

FIG. 59 is a sectional view taken along line Y1-Y1 in FIG. 57;

FIG. 60 is a circuit diagram of an example of an input and outputcircuit of a semiconductor device according to another embodiment of theinvention;

FIG. 61 is a plan view of a typical portion showing a device layout ofan input and output circuit cell of a semiconductor device according toanother embodiment of the invention; and

FIG. 62 is a plan view of a typical portion showing the peripheral powersupply device laid out in FIG. 61.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the description of the embodiments of the invention, the terms “madeof copper”, “copper used as a main wiring material” or “a material mademainly of copper” are intended to mean “the use of copper as a maincomponent”, for example. More particularly, it is a matter of coursethat impurities are usually present in copper of high purity. In thissense, to contain additives or impurities in members made of copper isnot excluded herein. Moreover, such expressions as mentioned aboveinclude those built-up structures wherein a metal layer made of amaterial other than copper is formed on a surface of a member made ofcopper. This is not limited only to copper, but is true of other typesof metals, such as, for example, aluminum, titanium nitride and thelike. Although, in the description of the invention, the subject mattermay be divided into a plurality of sections or embodiments, ifexpediently necessary, these divisions are not to be considered mutuallyirrelevant to one another unless otherwise stated. More particularly,one may be in the relation of a modification, details, supplementalexplanation and the like of part or all of the others. In the followingexamples, where reference is made to a number of elements (including thenumber, numerical value, quantity, range and the like), they should notbe construed as limited to specified values or numbers, respectively,except in the case where they are specified or limited to a specificvalue apparently in principle. That is, those values smaller or largerthan the respective specified values may also be within the scope of theinvention. Moreover, it is as a matter of course that constituentelements (including steps) in the following embodiments are not alwaysessential, except in the case where otherwise specified or where suchelements are considered to be apparently essential in principle.Likewise, if reference is made to the shape, positional relation and thelike of constituent elements, then substantially the like or similarshapes and the like are also within the scope of the invention, exceptin the case where otherwise specified or where such shapes should not beapparently included in principle. This is also true of theabove-indicated numbers and ranges. Throughout the drawings, likereference numerals indicate like parts or members having the samefunction, and a repeated explanation thereof is omitted. In thedrawings, plan views may be hatched in some cases for ease inunderstanding the subject matter. In the embodiments, MIS-FET (metalinsulator semiconductor field effect transistor) is referred to simplyas MIS, p-channel MIS-FET is referred to as pMIS, and n-channel MIS-FETis referred to as nMIS. The embodiments of the invention will bedescribed in detail with reference to the accompanying drawings.

Embodiment 1

The problem discovered for the first time by us will be described withreference to FIG. 1. FIG. 1 is a sectional view showing a typicalportion of a semiconductor device in the course of the manufacturethereof. A semiconductor substrate (hereinafter referred to simply as asubstrate) 50S of a wafer 50W is made, for example, of silicon (Si)single crystal and is electrically connected to a ground potential G atthe back side thereof. The figure shows a state where a four-layeredwiring structure is formed on the main surface (device-forming surface)of the substrate 50S. This four-layered wiring structure has a wiring 51and an insulating film 52. The wiring 51 is made of a metal which ismainly composed, for example, of aluminium. A wiring portion 51A of thewiring 51 is electrically connected to the substrate 50S. On the otherhand, a wiring portion 51B having a great wiring length (e.g. about 500μm or over) is in a floating state (i.e., electrically unconnected orfloating wiring) because of the fact that the semiconductor device is inthe course of the manufacturing process. These wirings 51A and 51B arearranged in a proximate condition as a second wiring layer. Theinsulating film 52 is made, for example, of silicon oxide (SiO₂ or thelike) and has the function of insulating the wirings 51. The existinginsulating film 52 is provided for complete insulation.

Under these circumstances, if the insulating film 52 is cleaned on theupper surface thereof, for example, with a brush BR, then an electriccharge is generated on the upper surface of the insulating film 52 byelectrostatic action, thereby causing the wiring 51 to be charged. Thischarging phenomenon is not limited to the cleaning with the brush BR,but is experienced through other processings as well, including, forexample, spin cleaning with pure water, dry etching of wirings per se,plasma treatment for removing a photoresist film by ashing, and thelike. If a charge accumulation in the wiring 51 exceeds a given level, adischarge takes place between the wirings 51A and 51B. Moreparticularly, the electric charge accumulated in the floating wiring 51Bruns, as shown by the arrows in FIG. 1, into the wiring portion 51A,which is connected to the ground potential G through the insulating film52 and is lower in potential. At this time, a very high potentialdifference occurs between the wirings 51A and 51B owing to the chargeaccumulated in the wiring portion 51B, so that neighboring portions ofthe wirings 51A, 51B are instantaneously subjected to a high potentialdifference of several hundreds to several thousands of volts, therebypermitting a high heating temperature as high as one thousand andseveral hundreds of degrees centigrade to be generated. This causes thewirings 51A, 51B to be deformed at the neighboring portion thereof, withthe attendant problem that the wirings 51A, 51B undergo short-circuitingat the neighboring portion. Especially, this problem is liable to beencountered in a case where, because a long wiring is apt to accumulatean electric charge, at least one of the wirings has a great wiringlength. The short-circuiting is apt to occur at a neighboring portion ofwirings having a high potential difference relative to each other, suchas a portion between the wiring 51A connected to the ground potential Gand the floating wiring 51B. Moreover, this becomes obvious when theadjacent space of the wirings 51 is rendered narrow as a result of ahigh degree of integration of the wirings 51 (according to our study,this has been frequently experienced when the space is at a pitch ofabout 0.8 μm or below). Such a problem as set out hereinabove is onethat has been confirmed by us for the first time. At present, theexistence of a long wiring and such a wiring connection in the course ofthe manufacture of a semiconductor device as set forth above (i.e. oneof the wirings is connected to a ground potential and the other is in afloating connection condition) have never been taken into account in theart.

To avoid the above-mentioned problem, according to this embodiment, afilm through which a minute electric current passes is used as theinsulating film between the wirings. In this way, discharge is enabledat a stage where a charge accumulation in the wirings is low. Thus, heatgeneration can be suppressed to a low level, thereby suppressing orpreventing a failure in short-circuiting between the wirings. This canlead to improved yield and reliability of semiconductor devices. Theimproved yield of semiconductor device results in an expected reductionin the cost of the device. This will be more particularly describedbelow.

FIG. 2 shows an example of a semiconductor device according Embodiment1, and FIG. 3 shows an enlarge, sectional view of the region A of FIG.2. A substrate 1S is made, for example, of silicon (Si) single crystal.The substrate 1S has on the main surface thereof (device-formingsurface) a groove isolation 2, such as SGI (shallow groove isolation) orSTI (shallow trench isolation), formed therein. This isolation 2 isformed, for example, by burying a silicon oxide film in a groove formedin the main surface of the substrate 1S. Moreover, a p-well PWL and ann-well NWL, respectively, are formed at the main surface side of thesubstrate 1S. For example, boron is introduced into the p well PWL andphosphorus is introduced into the n well NWL. At the active regions ofthe p well PWL and the n well NWL defined with the isolation 2, devicessuch as nMISQn and pMISQp are formed. The nMISQn has an n-typesemiconductor region 3N for source and drain, a gate insulating film 4and a gate electrode 5. The pMISQp has a p-type semiconductor region 3P,a gate insulating film 4 and a gate electrode 5. The gate insulatingfilm 4 is made, for example, of a silicon oxide film. The gate electrode5 is constituted, for example, of a polysilicon film alone, anarrangement of a silicide film, such as cobalt silicide or the like,formed on a polysilicon film, or a built-up arrangement wherein a metalfilm, such as tungsten or the like, is built up on a polysilicon filmthrough a barrier film, such as of tungsten nitride or the like.

The substrate 1S has, for example, a five-layered wiring structureformed on the main surface thereof. The five-layered wiring structurehas a wiring portion 6 and an insulating portion 7. The wiring portion 6has a wiring 6 a formed between adjacent layers of the respective wiringlayers M1 to M5 and a plug 6 b between adjacent wiring layers or betweenthe wiring and the substrate. The wiring 6 a may be formed, for example,of a single conductor film made of aluminium (Al), analuminium-silicon-copper (Cu) alloy, an aluminium-silicon alloy, aaluminium-copper alloy or the like. In this embodiment, a case where abuilt-up film made up of conductor films 6 a 1, 6 a 2 and 6 a 3 isillustrated. The lowermost, relatively thin conductor film 6 a 1 is afunctional film, which has the function of suppressing or preventing,for example, the constituent atoms of the wiring 6 a and the substrate1S from being diffused and also the function of improving the adhesionbetween the wiring 6 a and the insulating portion 7. The film 6 a 1 isconstituted, for example, of a single film of titanium nitride (TiN) ora built-up film of titanium formed on titanium nitride. The relativelythick conductor film 6 a 2 formed thereon is formed of a single film ofa conductor, which is made of a main wiring material including, forexample, aluminium (Al) or an aluminium-silicon-copper (Cu) alloy. Theuppermost, relatively thin conductor film 6 a 3 is a functional film,which has, aside from the functions of the above-mentioned conductorfilm 6 a 1, the function of reducing or preventing halation uponexposure to light for the formation of wiring, and it is formed, forexample, of a single film of titanium nitride or a built-up film oftitanium nitride built up on titanium. The plug 6 b is a wiring portionfor electrical connection between adjacent wirings 6 a of the wiringlayers M1 to M5 or between the wiring 6 a of the wiring layer M1 and thesubstrate 1S, and it is formed by burying a metal film, such as, forexample, tungsten, in a groove, such as a contact hole CH orthrough-hole TH, formed in the insulating portion 7. The plug 6 b may beconstituted of a metal film, such as tungsten, and a conductor film,such as titanium nitride, which is formed relatively thinly around theouter periphery (side surface and bottom surface) of the metal film.Although not limitative, the adjacent pitch of the wirings 6 a of thewiring layers M1 to M3 is, for example, at 0.52 μm. The adjacent pitchof the wirings of the wiring layers M4, M5 is, for example, at 1.04 μm.

The insulation portion 7 is fundamentally constituted, for example, ofan insulating film (second insulating films) 7 a (7 a 1 to 7 a 6), suchas, for example, a silicon oxide film. At the respective insulatingportions of the wiring layers M1 to M5, an insulating film (firstinsulating films) 7 b (7 b 1 to 7 b 5), whose conductivity is higherthan that of the insulating film 7 a, is provided for direct contactwith the wiring 6 a of the respective wiring layers M1 to M5 and theplug 6 b. In the figure, a structure wherein the insulating film 7 b isso deposited as to cover the surfaces (side and upper surfaces) of thewiring 6 a is shown. Although not shown in the figure, the insulatingfilm 7 b is so provided as to cover and be in contact with a guard ringformed in the vicinity of an outer periphery of a semiconductor chip asextending along the outer periphery. The insulating film 7 b functionsto insulate the adjacent wirings 6 during the normal operation of thesemiconductor device and has the function of permitting a minuteelectric current to pass between adjacent wiring portions 6 uponapplication of an overvoltage, which is higher than a working voltage ofthe semiconductor device. More particularly, as described hereinafter,the insulating film 7 b has a low electrical conductivity sufficient toinsulate the wiring portions 6, like the insulating film 7 a, within avoltage range (i.e. a voltage of about 20 V or below) of the normaloperation of the semiconductor device, thus functioning to insulate thewiring portions 6, like the insulating film 7 a. At an overvoltage,which is higher than a working voltage of the semiconductor device, theinsulating film 7 b has the function of permitting a minute electriccurrent to pass between adjacent wiring portions 6, thereby renderingthe wiring portions 6 conductive. The provision of such an insulatingfilm 7 b allows the electric charge accumulated in the wiring portion inthe course of the manufacture of the semiconductor device to escape tothe adjacent wiring portion 6 and the substrate 1S through theinsulating film 7 b at a stage where the charge accumulation is low.More particularly, the charge can be discharged at a low accumulation atthe wiring portion 6, so that the heat release value generated by thedischarge between the adjacent wiring portions 6 can be suppressed to alow level. The thickness of the insulating film 7 a is, for example, atabout 30 nm. With the structure of FIG. 3, if the insulating film isformed so as to be too thick, adjacent wirings 6 a, 6 a along thehorizontal direction, as viewed in FIG. 3, may not be buried with theinsulating film 7 a in some cases. If the thickness of the insulatingfilm 7 b is at about 30 nm, then such a burying failure can be avoided.According to an experiment made by us, it has been difficult from theviewpoint of film formation to form the insulating film to a thicknessof 30 nm or below. Mention is made, as a material for the insulatingfilm 7 b, of a silicon-rich silicon oxide film or a silicon nitride(SiON) film, for example. The silicon-rich silicon oxide film is onewherein the composition of the silicon oxide film is represented bySixOy, wherein y/x<2. It has been accepted that the conductivity of asilicon-rich silicon oxide film is ten times higher than that of anordinary silicon oxide film (SiO₂). It is known that when silicon isintroduced into an insulating film (silicon oxide film), theconductivity of the insulating film usually increases and the refractiveindex of the insulating film becomes high. Accordingly, for measurementof the electrical characteristics of insulating films, a measurement ofthe refractive index of these films for comparison permits theelectrical characteristics for different contents of silicon in theinsulating films to be measured. More particularly, according to thisembodiment, an insulating film having a high refractive index means aninsulating film having a high silicon content or an insulating filmhaving a high conductivity.

FIGS. 4 to 7 show the results of measurement of a current I-voltage Vcharacteristic of silicon oxide films. FIG. 4 shows the I-Vcharacteristic of ordinary silicon oxide (SiO₂), and FIGS. 5 to 7,respectively, show an I-V characteristic in the case where therefractive index n and film thickness t of silicon-rich silicon oxidefilms are changed. The reason why plural curves are depicted in eachfigure is that plural chips within a wafer subjected to an experimentunder the same conditions are measured. FIG. 8 shows, for comparison,the relation between the refractive index and the electric current ofabout 30 μm thick silicon oxide films derived from the results of FIGS.4 to 7. Moreover, FIG. 9 shows the relation between the thickness andthe electric current of a silicon-rich silicon oxide film having arefractive index of 1.55. According to FIGS. 4 to 9, it will be seenthat a silicon-rich silicon oxide film is more likely to pass anelectric current than the ordinary silicon oxide film. It will also beseen that a greater thickness t of the silicon-rich silicon oxide filmallows an electric current to be run more greatly. In addition, a higherrefractive index n, i.e. a higher content of silicon on the siliconoxide film, makes the electric current pass more greatly. According tothe studies made by us, where a silicon-rich silicon oxide film having arefractive index of 1.55 or over is used as a material for theinsulating film 7 b, good results are obtained in order to avoid theproblem concerning the short-circuiting failure between the wirings.

FIG. 10 shows the results of measurement of the I-V characteristic of asilicon oxynitride film (SiON). This film is more likely to allow anelectric current to pass therethrough than the ordinary silicon oxidefilm (FIG. 4) and the silicon-rich silicon oxide films (FIGS. 5 to 7).In this embodiment, it is possible to use such a silicon oxide film(SiON) as a material for the insulating film 7 b. In this case, as shownin FIG. 10, this film is more likely to pass an electric current thanthe silicon-rich silicon oxide film, and it exhibits a higherconductivity. Thus, better results are obtained in order to avoid theproblem concerning the failure of short-circuiting between the wirings.

Next, an example of a method of manufacturing the semiconductor deviceof Embodiment 1 will be described.

Initially, an example of a cleaning device of the type used in thecourse of manufacture of the semiconductor device of Embodiment 1 isshown in FIG. 11. A cleaning device 10 is one wherein foreign matter Pis removed from a cleaned surface of a wafer 1W obtained after a desiredtreatment and has a stage 10 a, a nozzle 10 b, a brush BR and a brushholder 10 c. The cleaning treatment is carried out in the followingmanner, for example. First, the wafer 1W is mounted in a temporarilyfixed state so that the surface of the wafer 1W to be cleaned is inface-to-face relation with the brush BR side. Subsequently, whilerotating the stage 10 a, a cleaning fluid, such as pure water, issupplied from the nozzle 10 b toward the surface of the wafer 1W to becleaned. In this condition, the brush BR is rubbed against the surfaceof the wafer 1W while spinning the brush BR by rotation of the brushholder 10 c, and it is moved from one end to the other of the wafer 1Walong the direction of arrow B in FIG. 11, thereby removing the foreignmatter P from the surface of the wafer 1W.

Next, an example of a manufacturing process used in the production ofthe semiconductor device of Embodiment 1 will be described withreference to FIGS. 12 to 16, which show a sectional view of a typicalpart of the wafer during steps in the manufacture of the semiconductordevice, respectively. FIG. 12 is a sectional view of a typical part ofthe wiring layers M2, M3 in the wafer 1W during the course ofmanufacture of the semiconductor device. The wiring layer M2 has aninsulating film 7 b 2 formed by a CVD (chemical vapor deposition) methodto be described hereinafter so as to cover the wiring 6 a therewith. Aninsulating film 7 a 3 is deposited on the insulating film 7 b 2 by a CVDmethod described hereinafter. The insulating film 7 a 3 of the wiringlayer M2 is flattened on the upper surface thereof by a CMP (chemicalmechanical polishing) method, on which conductor films 6 a 1, 6 a 2, 6 a3 for the wiring formation of the wiring layer M3 are, respectively,deposited by a sputtering method or the like. These conductor films 6 a1, 6 a 2, 6 a 3 are subjected to patterning by an ordinaryphotolithographic technique (hereinafter referred to simply aslithography) and also by a dry etching technique (hereinafter referredto simply as dry etching), thereby forming the wiring 6 a at the wiringlayer M3, as is particularly shown in FIG. 13.

Thereafter, as shown in FIG. 14, the insulating films 7 b 3, 7 a 4 aredeposited on the wiring layer M3 in this order according to a CVDmethod, and the upper surface of the insulating film 7 a 4 is flattenedby a CMP method. Thereafter, the upper surface (surface to be cleaned)of the insulating film 7 a 4 is cleaned by means of the cleaning device10 (see FIG. 11) using the brush BR, thereby removing foreign matterfrom the insulating film 7 a 4. At this stage, the charge generated inthe upper surface of the insulating film 7 a by the electrostatic actionis accumulated in the wiring 6 a of the respective wiring layers M1 toM3, so that an electric current passes from the floating wiring 6 a tothe wiring 6 b connected to the substrate 1S. In this embodiment,however, the insulating film 7 b (7 b 1 to 7 b 3) whose conductivity ishigher than that of the insulating film 7 a (7 a 1 to 7 a 4) isprovided, so that the charge accumulated in the wiring 6 a can escapethrough the insulating film 7 b (7 b 1 to 7 b 3) to the ground potentialG. Thus, the charge can be discharged at a stage where the chargeaccumulation in the wiring 6 a is low, thereby making it possible tolower the heat release value generated by the discharge. Thus, ashort-circuiting failure between the wirings 6 a and 6 a can besuppressed or prevented. This leads to improved yield and reliability ofthe semiconductor device. The improved yield of semiconductor device inturn leads to an expected cost reduction of the device.

Next, as shown in FIG. 15, a through-hole TH is formed in the insulatingfilms 7 a 4, 7 b 3 by lithography and dry etching, followed bydeposition of a film of a high melting point metal, such as, forexample, tungsten, on the main surface of the wafer 1W. The high meltingpoint metal film is polished by a chemical mechanical polishing methodso that the film is left only within the through-hole TH, therebyforming a plug 6 b in the through-hole TH. Subsequently, the polishedsurface is cleaned by means of the cleaning device to remove foreignmatter therefrom. In this way, a short-circuiting failure between thewirings can be suppressed or prevented by such an action as set forthhereinabove.

As shown in FIG. 16, after forming the wiring 6 a of the wiring layer M4in the same way as the wiring 6 a of the wiring layer M3, an insulatingfilm 7 b 4 is deposited, by a CVD method to be described hereinafter,over the entire main surface of the wafer 1W so as to cover the wiring 6a of the wiring layer M4 therewith. Thereafter, the uppermost wiringlayer M5 is formed in the same way as stated hereinabove, therebycompleting a semiconductor device through an ordinary manufacturingprocess of the semiconductor device.

Next, an example of a film-forming procedure used in formation of theinsulating film 7 b (7 b 1 to 7 b 5) is illustrated. A case where theinsulating film 7 b is formed of a silicon-rich silicon oxide film willbe described. FIG. 17 shows an example of film-forming sequences of theinsulating films 7 a, 7 b in the case where the insulating film 7 b isformed of a silicon-rich silicon oxide film. It will be noted that thefigures in the sequences of gases in FIG. 17, respectively, indicatefeeds of gases (unit: sccm=cm³/minute), and the figures in the sequencesof “upper electrode HF power and lower electrode LF power” indicate highfrequency power (unit: W), respectively.

In this embodiment, the insulating film 7 b is formed by a plasma CVDmethod using, for example, a silane gas. The plasma CVD apparatus beingused is, for example, of a parallel plate type. For a treating gas, amixture of a silane gas, such as, for example, monosilane (SiH₄) or thelike, oxygen (O₂) and a diluent gas, such as Ar or the like, is used.Other types of silane gas, such as disilane (Si₂H₆), TEOS(tetraethoxysilane) or the like, may be used in place of monosilane.Likewise, an oxygen-containing gas, such as nitrous oxide (N₂O), ozone(O₃) or the like, may be used instead of oxygen. The time period of t0to t1 indicates an idling time, the time period of t2 to t5 indicates afilm-forming time for the insulating film 7 b, and the time period of t5to t8 indicates a film-forming time for the insulating time 7 a. Alongwith the wafer 1W starting to be heated from time t1, argon and oxygenbegin to be fed into the treating chamber. From time t2, the feed ofmonosilane into the chamber is started. In this embodiment, in order torender the insulating film 7 b rich in silicon, the flow rate ofmonosilane during the course of film formation of the insulating film 7b is larger than that used for the insulating film 7 a. The flow rate ofmonosilane for the formation of the insulating film 7 b is, for example,at about 77 sccm (=77 cm³/minute), that of oxygen is, for example, atabout 97 sccm, and that of argon is, for example, at about 90 sccm. Onthe other hand, the flow rate of monosilane for the formation of theinsulating film 7 a is, for example, at about 70 sccm, that of oxygenis, for example, at about 90 sccm, and that of argon is, for example, atabout 90 sccm. In this way, where the insulating film 7 b is formed of asilicon-rich silicon oxide film, the insulating films 7 a, 7 b can beformed within the treating chamber of the same plasma CVD apparatus.Thus, the time required for film formation can be reduced. In addition,the insulating films 7 a, 7 b can be formed in a continuous, stablestate, and occasions of contamination with foreign matter can be reducedin number, thereby improving the reliability of the film formation.

Where the insulating film 7 b is formed of silicon oxynitride (SiOX), aplasma CVD method using, for example, a silane gas is also used. For atreating gas, a mixed gas consisting of a silane gas, such as monosilane(SiH₄) or the like, nitrous oxide (N₂O) and a diluent gas, such ashelium (He) or the like, is used. Other types of silane gas, such asdisilane (Si₂H₆), TEOS (tetraethoxysilane) or the like, may be used inplace of monosilane. Ammonia or ammonia and nitrogen may be furtheradded to the above-mentioned mixed gas. If ammonia or nitrogen is added,oxygen (O₂) or ozone (O₃) may be used in place of nitrous oxide. Theflow rate of monosilane for the film formation is, for example, at about50 sccm, that of nitrous oxide is, for example, at about 66 sccm, andthat of helium is, for example, at about 1500 sccm. The temperature ofthe wafer 1W during the film formation is, for example, at about 350°C., and the pressure within the chamber is, for example, at about 5Torr. (=666.612 Pa).

Embodiment 2

In Embodiment 2, there is a modification of the wiring structure. FIG.18 shows a sectional view of an essential part of a semiconductor devicerepresenting Embodiment 2 at the same portion as region A of FIG. 3. InEmbodiment 2, the insulating film 7 b (7 ba to 7 b 5) of the respectivewiring layers M1 to M5 are formed as an underlying layer of the wiring 6a. More particularly, the wiring 6 a is formed on the insulating film 7b (7 b 1 to 7 b 5) in the respective wiring layers M1 to M5. InEmbodiment 2, the lower surface of the wiring 6 a and the upper sidesurface of the plug 6 b are in contact with the insulating film 7 b (7 b1 to 7 b 5), respectively. Accordingly, similar results as described inEmbodiment 1 can be obtained in Embodiment 2. With this structure, it isnot necessary to take into account the burying properties when aninsulating film is buried between adjacent wirings 6 a, 6 a of the samewiring layer, and, thus, the insulating film 7 b can be made thickerthan in the case of Embodiment 1. This eventually leads to an increasedconductivity of the insulating film 7 b, thereby ensuring improvedstatic elimination.

An example of the manufacturing process used in the formation of asemiconductor device according to Embodiment 2 is illustrated withreference to FIGS. 19 to 23, which are, respectively, sectional views ofa wafer during steps in the manufacture of a semiconductor device. FIG.19 is a sectional view of the wiring layer M1 in the wafer 1W in thecourse of manufacture of the semiconductor device of FIG. 18. Thefirst-layer wiring 6 a is formed on the insulating film 7 b 1 of thewiring layer M1. This wiring 6 a is covered with the insulating film 7 a2. Next, the insulating film 7 b 2 is deposited, as shown in FIG. 20, onthe insulating film 7 a 2 of the wiring layer M1 in the same manner asin the foregoing Embodiment 1. Subsequently, as shown in FIG. 21, athrough-hole TH is formed in the insulating films 7 b 2 and 7 a 2 bylithography and dry etching, followed by formation of the plug 6 b inthe through-hole TH in the same manner as in Embodiment 1. Thereafter,as shown in FIG. 22, the wiring 6 a for wiring layer M2 is formed overthe insulating film 7 b 2 as similar to the first embodiment; and,thereafter, the insulating later 7 a 3 is deposited so as to cover thewiring 6 a, and, further, the insulating film 7 b 3 is deposited asshown in FIG. 23. With respect to the wiring layers M4, M5, a similarprocedure is repeated to complete a semiconductor device using anordinary process of manufacture of a semiconductor device. In the caseof this structure, cleaning is carried out by means of the cleaningdevice 10 (see FIG. 11) using the brush BR after the step of forming theplug 6 b or after the deposition of the insulating films 7 a, 7 b. Asstated hereinbefore, a charge is accumulated in the wiring layer 6 a ofthe respective wiring layers M1 to M3 by electrostatic action, and itwill run from the floating wiring 6 a to the wiring 6 a that isconnected to the substrate 1S. In this Embodiment 2, the insulating film7 b is provided, so that the charge accumulated in the wiring 6 a isable to escape via the insulating film 7 b to the ground potential G.Thus, the charge can be discharged when its accumulation is low, so thatthe heat release value generated by the discharge can be suppressed to alow level. Thus, short-circuiting failure between the wirings issuppressed or prevented. Accordingly, the yield and reliability of theresulting semiconductor device can be improved. The improved yield ofthe semiconductor device leads to an expected cost reduction of thesemiconductor device.

Embodiment 3

In Embodiments 1 and 2, the case where the insulating film 7 b isprovided in all the wiring layers M1 to M5, respectively, has beenillustrated, but the invention is not limited to this case, since theinsulating film 7 b may be provided only in selected wiring layers. Forinstance, the wiring short-circuiting failure is liable to occur when along wiring (of about 500 μm or over) exists. In this sense, theinsulating film 7 b may be provided only in the uppermost wiring layerand a wiring layer provided therebeneath (e.g. all or selected layers ofthe wiring layers M4, M5), where a long wiring exists relativelyfrequently. Moreover, because the wiring short-circuiting failure is aptto occur at a portion where the space between adjacent wirings is narrow(e.g. at a portion where the adjacent wiring pitch is at 0.8 μm orbelow), the insulating film 7 b may be provided only in the wiringlayers having a portion wherein the space between adjacent wirings isnarrow (e.g. all or selected layers of the wiring layers M1, M2 and M3).In addition, the insulating film 7 b may be arranged, for example, onlyin the odd or even wiring layers. For instance, taking into account botha long wiring and the adjacent wiring space, the insulating film 7 b maybe provided only in the wiring layers M2, M4. Where a wiring layer mademainly of aluminium and a wiring layer made mainly a high melting metalexists among the wiring layers, the insulating film 7 b is provided inthe aluminum-based wiring layer, but it is not provided in the highmelting metal-based wiring layer. In this case, the insulating film 7 bmay be provided in all layers of the aluminium-based wiring layer.Alternatively, the insulating film 7 b may be formed at selected wiringlayers alone among plural wiring layers made mainly of aluminium.

According to Embodiment 3, the deposition steps used in formation of theinsulating film 7 b can be reduced in number, so that the wiringshort-circuiting failure is suppressed or prevented from occurringbecause of the reduced number of processing steps.

Embodiment 4

In Embodiment 4, there is a modification of the wiring structure. FIG.24 is a plan view of the wiring 6 a of the wiring layers M2, M3, andFIG. 25 is a sectional view, taken along line X1-X1 in FIG. 24. Thewiring 6 a of the wiring layer M2 is formed so as to be wider (in adog-bone shape), at a portion which is connected with the wiring 6 a ofthe wiring layer M3, than other portions thereof, while taking adiscrepancy in alignment of the through-hole TH into account. In aconventional wiring forming technique, an insulating film serving as anetching stopper is provided, in some cases, so as to cover the wiringtherewith while taking discrepancy in alignment into consideration. Withthe dog bone shape, no discrepancy of the alignment takes place, so thatit is not necessary to provide any insulating film used for an etchingstopper. In this embodiment, the insulating film 7 b which is providedso as to cover the wiring 6 a of the wiring layer M2, as shown in FIG.25, is provided only for the discharge described hereinbefore.

On the other hand, as shown in the sectional view of FIG. 26, with thewidth of the wiring 6 a being substantially as narrow as thethrough-hole TH, when the position of the through-hole TH is formed soas to be shifted relative to the wiring 6 a, it may be, in some case,that the insulating film 7 b exposed from the bottom of the through-holeTH and the underlying insulating film 7 a are etched. To avoid this, aninsulating film 7 c for use as an etching stopper is provided so as tobe superposed on the insulating film 7 b, as shown in FIG. 27. Theinsulating film is provided so as to escape the charge accumulated inthe wiring 6 a and should preferably be in contact with the wring 6 a.The procedure used in forming the through-hole in this case isillustrated with reference to FIGS. 28 to 30.

First, as shown in FIG. 28, a through-hole TH1 is formed using aphotoresist pattern (hereinafter referred to simply as a resist pattern)R1 as an etching mask. At this time, the etching selection ratio of theinsulating films 7 a and 7 c is so great that the insulating film 7 a isremoved under conditions where the insulating film 7 a is more likely tobe etched. Subsequently, as shown in FIG. 29, when the insulating filmis exposed, the insulating film 7 c is removed under conditions wherethe insulating film 7 c is more likely to be etched than the insulatingfilm 7 a, thereby forming a through-hole TH2. Finally, the insulatingfilm 7 b, which is exposed from the bottom of the through-hole TH2, isetched, thereby forming a through-hole TH, wherein part of the wiring 6a is exposed, as shown in FIG. 30. In this case, the insulating film 7 bmay be etched more deeply than the upper surface of the wiring 6 a at adiscrepancy portion of alignment between the through-hole TH and thewiring 6 a.

Next, FIG. 31 shows an example of the case where Embodiment 4 is appliedto the wiring structure of Embodiment 2. In this case, the insulatingfilm 7 a for use as an etching stopper is deposited so as to cover thewiring 6 a therewith, on which the insulating film 7 a is furtherdeposited. If the alignment discrepancy between the through-hole TH andthe wiring 6 a takes place, excess etching does not occur. Next, FIG. 32shows a modification of the wiring structure of Embodiment 4. In thiscase, the insulating film 7 c for use as an etching stopper is formed asan underlying layer of the wiring 6 a. More particularly, the insulatingfilm 7 c is formed on the insulating film 7 a, on which the wiring 6 ais formed, on which the insulating film 7 b for discharge is furtherdeposited so as to cover the wiring 6 a therewith. In this connection,when an alignment discrepancy arises between the through-hole TH and thewiring 6 a, the insulating film 7 b at the discrepancy may be etched.Nevertheless, the existence of the underlying insulating film 7 cprevents the underlying insulating film 7 a from being etched.

Embodiment 5

In connection with Embodiment 5, application to an element layer will bedescribed. FIG. 33 is a sectional view of a typical portion in thecourse of manufacture of a semiconductor device for illustrating theproblem checked by us. Reference numeral 52 a indicates an insulatingfilm, reference numeral Q50 indicates a MIS, reference numeral 53indicates a gate insulating film, and reference numeral 54 indicates agate electrode. The charge and discharge phenomena of such a wiringarrangement as mentioned above involve, aside from the problem ofshort-circuiting failure between the wirings, a problem of inducingbreakage of the gate insulating film 53 provided beneath the gateelectrode 54 connected to a long wiring 51B. To avoid this, it isnecessary to design the wiring connected to the gate electrode 54 so asto be short. This undesirably requires a larger number of connectionwirings, with the attendant problem that the area of wirings increases,thereby leading to an increasing chip size. It is to be noted that thearrow in FIG. 33 indicates the path escape of an electric charge.

In such a case as set out above, when using the arrangements illustratedfor the foregoing Embodiments 1 to 4, discharge is caused to take placebetween adjacent wirings prior to the breakage of the gate insulatingfilm, so that the breakage of the gate insulating film can be reduced orprevented. In this connection, however, the following arrangement isalso possible. More particularly, a structure may be used wherein anelectric charge is allowed to escape from the gate electrode to thesubstrate.

FIG. 34 indicates a specific arrangement for this. A sidewall 11 a isformed on the side surfaces of the gate electrode 5. The side surface ofthe sidewall 11 a is in direct contact with the gate electrode 5, andthe bottom of the sidewall 11 a is also in direct contact with thesubstrate 1S. The sidewall 11 a is formed of an insulating film similarto the insulating film 7 b. In this way, according to Embodiment 5, theelectric charge passing through the wiring to the gate electrode 5 isallowed to escape, as shown by arrow C, from the side surface of thegate electrode 5 through the sidewall 11 a to the substrate 1S.Accordingly, the breakage of the gate insulating film ascribed to thecharging phenomenon in the wiring can be suppressed or prevented. As aconsequence, the wiring connected to the gate electrode 5 can beelongated, thereby reducing the number of connection wirings with thepossibility of reducing the chip size. This sidewall 11 a is formed byforming the gate electrode 5, depositing an insulating film for formingthe side wall 11 a on a wafer, and etching back the insulating filmusing an anisotropic dry etching technique.

FIG. 35 shows a modification of FIG. 34. In this instance, theinsulating film 7 d for use as an etching stopper is deposited on themain surface of the substrate 1S so as to cover the gate electrode 5 andthe sidewall 11 a. The insulating film 7 d is made, for example, of asilicon nitride film. In doing so, not only will such effects asobtained in FIG. 34 be obtained, but also the problem ascribed to thealignment discrepancy of the contact hole CH can be mitigated oravoided. More particularly, if the position of the contact hole CH isshifted, the gate electrode is prevented from being exposed therefrom.This ensures an improved yield of the semiconductor device.

FIGS. 36 and 37 show another modification of FIG. 34. FIG. 37 shows thecase where the contact hole CH and the plug 6 b are, respectively,formed in FIG. 36. In this case, the sidewall 11 b at the side surfaceof the gate electrode 5 is made, for example of a silicon nitride filmor silicon oxide film. The insulating film 7 b for discharge isdeposited on the main surface of the substrate 1S so as to cover thegate electrode 5 and the sidewall 11 b therewith. In this case, thecharge flowing through the wiring to the gate electrode 5 can escape, asshown by arrow D, from the upper surface of the gate electrode 5 throughthe insulating film 7 b to the substrate 1S. The formation of thesidewall 11 b with a silicon nitride film can mitigate or avoid theproblem caused by the alignment discrepancy at the contact hole CH. Inthis case, the sidewall is formed by etching back, after which theinsulating film 7 b is deposited as stated hereinabove.

FIGS. 38 and 39 show a further modification of FIG. 34. FIG. 39 shows asection transverse to the section of FIG. 38. In this modification, acap insulating film 12 a, that is made, for example, of a silicon oxidefilm or silicon nitride film, is formed on the gate electrode 5. Theinsulating film 7 b for discharge is deposited on the main surface ofthe substrate 1S so as to cover the sidewall 11 b and the cap insulatingfilm 12 therewith. In this case, the charge passing through the wiringto the gate electrode 5 can escape, as shown by arrow E, from a portionin contact with the insulating film 7 b of the plug 6 b within thecontact hole CH to the substrate 1S. If the sidewall 11 b and the capinsulating film 12 a, respectively, are formed of a silicon nitridefilm, or if the insulating film 7 d for use as an etching stopper isformed as in FIG. 35, the problem ascribed to the alignment discrepancyat the contact hole CH can be mitigated or avoided.

FIG. 40 shows a still further modification of FIG. 34. In thismodification, the insulating film 7 b for discharge is formed so as tocover the gate electrode 5 at side and upper surfaces thereof. Thisinsulating film 7 b is in contact with the side and upper surfaces ofthe gate electrode 5, and it is also in contact with the main surface ofthe substrate 1S. The gate electrode 5 has the sidewall 11 b formedthrough the insulating film 7 b at the side surfaces thereof. In thiscase, the charge passing through the wiring to the gate electrode 5 canescape, as shown by arrow F, from the side and upper surfaces of thegate electrode 5 through the insulating film 7 b to the substrate 1S. Ifthe sidewall 11 b is formed of a silicon nitride film, or if theinsulating film 7 d is formed as shown in FIG. 35, then the problemascribed to the alignment discrepancy of the contact hole CH can bemitigated or avoided. For the formation of such an arrangement as setout above, after formation of the gate electrode 5, the insulating 7 dis deposited on the wafer, followed by further deposition of aninsulating film for the formation of the sidewall 11 b and etching backthe insulating film for the formation of the sidewall 11 b using a dryetching technique.

It will be noted that, although applications to nMISQn have beenillustrated in Embodiment 5, this embodiment may be applied as well to apMISQp. The arrangement of Embodiment 5 exhibits good effects by itself,and when combined with the foregoing Embodiments 1 to 4, good resultsare also obtained from the standpoint of mitigating and preventing theshort-circuiting failure between wirings and the gate insulationbreakage.

Embodiment 6

In Embodiment 6, there is application of the invention to a Damascenewiring structure. FIG. 41 is a sectional view of an essential part of asemiconductor device according to Embodiment 6, and FIG. 42 is anenlarged, sectional view of a region G of FIG. 41.

A wiring portion 6 of a wiring structure in the semiconductor device ofEmbodiment 6 has a wiring 6 c of an undermost wiring layer M0, a wiring6 d provided in the respective intermediate wiring layers M1 to M4, awiring 6 a provided in an uppermost wiring layer M5, and a plug 6 b (6 b1 to 6 b 4) provided between adjacent wirings or a wiring and asubstrate. The wiring layers M0 to M4 are provided as a Damascene wiringstructure, respectively, and the uppermost wiring layer M5 is formed assuch an ordinary wiring structure as illustrated by the foregoingEmbodiments 1 and 2. The wiring 6 c of the undermost wiring layer M0 isformed so as to be buried within a wiring groove (i.e. an opening forwiring) 13, and it has a conductor film 6 c 1 for a main wiringmaterial, such as, for example, tungsten or the like, and a conductorfilm 6 c 2 for a barrier, such as titanium nitride (TiN) or the like,arranged to side and bottom surfaces of the conductor film for the mainwiring material. The wiring 6 d in the intermediate wiring layers M1 toM4 is formed so as to be buried within the wiring groove 13, and it hasa conductor film 6 d 1 for a main wiring material, such as of copper(Cu) or the like, and a conductor film 6 d 2 for a barrier that isprovided at the side and bottom surfaces of the conductor film for themain wiring material and is made of a single film or builtup film oftitanium nitride (TiN), tantalum (Ta) or tantalum nitride (TaN). Theplugs 6 b 1, 6 b 4 are, respectively, those illustrated in connectionwith the foregoing Embodiments 1 to 5. The plug 6 b 2 has a conductorfilm for main wiring material, such as, for example, copper, and aconductor for a barrier that is formed on the side and bottom surfacesof the conductor film for main wiring material and is made, for example,of a single film or built-up film of titanium nitride, tantalum ortantalum nitride. The plug 6 b 3 is formed integrally with the justabove wiring 6 d.

The insulating portion 7 has an insulating film 7 a (7 a 1 to 7 a 12),an insulating film 7 b (7 b 1 to 7 b 10) and insulating films 7 d, 7 e,7 f 1 and 7 f 2. The insulating films 7 a 1 to 7 a 11 may be made, asidefrom the materials exemplified in the foregoing Embodiment 1, of asingle film consisting of an insulating film of low dielectric constant(low-K insulating film), such as, for example, of SiOF, or a builtupstructure wherein a silicon oxide film or the like is deposited on thesingle film. The low-K insulating film is one which has a dielectricconstant that is lower than a silicon oxide film and is constituted byan insulating film of low dielectric constant having a dielectricconstant similar to a specific inductive capacity of ε=4.1 to 4.3 of theTEOS oxide film. Using the arrangement having the low-K insulating film,the dielectric constant of the insulating film 7 a can be lower ascompared to the case where the insulating film 7 a is formed of asilicon oxide film. For the low-K insulating film, an organic polymermaterial such as, for example, SILK (made by Dow Chemical Co., withspecific inductive capacity=2.7, heat-resistant temperature=490° C. orover, and dielectric breakdown voltage=4.0 to 5.0 MV/Vm) or FLARE (madeby Honeywell electric Materials, with specific inductive capacity=2.8and heat-resistant temperature=400° C. or over) of a polyallyl ether(PAE) material, or an organic silica glass (SiOC) material, such asHSG-R7 (made by Hitachi Chemical Co., Ltd., with specific inductivecapacity =2.8 and heat-resistant temperature=650° C.), Black Diamond(made by Applied Materials, Inc., with specific inductive capacity=3.0to 2.4 and heat resistant temperature=450° C.), p-MTES (made by HitachiDevelopment Co., Ltd., with specific inductive capacity=3.2) or the likemay be used. In this case, the dielectric constant can be lowered in asimilar way to that mentioned above.

The insulating film 7 e is a film which functions mainly as an etchingstopper and is made, for example, of silicon nitride (Si₃N₄ or thelike), silicon carbide (SiC) or silicon carbide nitride (SiCN). Thereason why the insulating film 7 e is used in the wiring layer M0without use of the insulating film 7 b for discharge is that the mainwiring material for the wiring 6 c of the wiring layer M0 is mainly madeof a high melting point metal, such as tungsten, so that no problem ofshort-circuiting failure between adjacent wirings ascribed to thedischarge arises. From this point of view, although the insulating film7 b 1 may be formed of the insulating film 7 e, the insulating film 7 b1 is connected via the plug 6 b 2 to the wiring 6 d made of copper inthe wiring layer M1 used as a main wiring material, and, thus, it isformed of the insulating film 7 b for discharge. The insulating film 7 b(7 b 1 to 7 b 10) is so arranged as to be in contact with the wirings 6d, 6 a and the plugs 6 b 2 to 6 b 4. In this manner, Embodiment 6ensures similar effects as those achieved in the foregoing Embodiments1, 2. The insulating films 7 a 12, 7 f 1, 7 f 2 are those films servingas a surface protecting film, wherein the insulating film 7 a 12 ismade, for example, of a silicon oxide film or the like, the insulatingfilm 7 f 1 is made, for example, of a silicon nitride film or the like,and the insulating film 7 f 2 is made, for example, a polyimide resinfilm or the like. The insulating films 7 a 12, 7 f 1, 7 f 2 are,respectively, formed at part thereof with an opening 14 through whichpart of the fifth-layer wiring 6 a is exposed. The portion (bonding padhereinafter referred to as pad) of the wiring 6 a exposed from theopening 14 is bonded with a bonding wire BW. In Embodiment 6, theinsulating film 7 b may be selectively formed in the wiring layers M1 toM4 using copper as a main wiring material, like Embodiment 3. Thisensures similar effects as in the foregoing Embodiment 3.

Next, an example of a method of manufacturing the semiconductor deviceaccording to Embodiment 6 will be described. FIG. 43 is a sectional viewof a typical part of the wafer 1W in the course of the manufacture ofsemiconductor device of Embodiment 6. In this figure, a case where thewiring 6 d in the first-layer wiring layer M1 has been formed by asingle Damascene method is shown. The insulating film 7 b is made, forexample, of silicon oxynitride (SiON) or the like. An insulating film 15a is made, for example, of a silicon oxynitride deposited on theinsulating 7 a 6. In this case, if, after deposition of the insultingfilm 15 a, the film is subjected to cleaning with a cleaning device 10(see FIG. 11) using the afore-indicated brush BR, an electric charge isaccumulated in the wiring 6 d of the wiring layer M1 by electrostaticaction, and the charge escapes from the upper surface side of the wiring6 d via the insulating films 7 b 2, 7 b 1 to the ground potential GP,thereby permitting the charge to be discharged at a stage where thecharge accumulation in the wiring 6 d is low. Thus, the heat releasevalue caused by the discharge can be suppressed to a low level.Accordingly, a short-circuiting failure between the wirings 6 d and 6 dusing copper as a main wiring material can be suppressed or prevented.

Subsequently, the insulating film 15 a is subjected to patterning bylithography and dry etching, as shown in FIG. 44, after which anantireflective film 16 a is deposited on the main surface of the wafer1W, followed by further formation of a resist pattern R2 for forming athrough-hole. Thereafter, the antireflective film 16 a and theinsulating films 7 a 6, 7 b 4, 7 a 5 are etched by use of the resistpattern R2 as an etching mask, thereby forming a through-hole TH, whichis substantially circular in plane view, as shown in FIG. 45. Thethrough-hole TH at this stage is not fully opened, with its bottom beingstopped at an intermediate portion of the insulating film 7 a 5 alongthe thickness direction thereof. Thereafter, the resist pattern R2 andthe antireflective film 16 a are removed, as shown in FIG. 46, afterwhich the insulating films 7 a 6, 7 a 5 are selectively etched using theinsulating film 15 as a mask in a condition where the insulating films 7b 4, 7 b 3 function as an etching stopper, thereby forming a wiringgroove 13 and the through-hole TH, as shown in FIG. 47. The through-holeTH at this stage is not yet fully opened, with its bottom being stoppedat the insulating film 7 b 3. Thereafter, the insulating films 15 a, 7 b3, 7 b 4 are selectively etched, respectively, thereby fully forming thewiring groove 13 and the through-hole (an opening for wiring) TH. Partof the upper surface of the wiring in the wiring layer M1 is exposedfrom the bottom of the through-hole TH. Next, a conductor 6 d 2 for abarrier, which is made, for example, of a single film of titaniumnitride or tantalum nitride or a builtup film thereof, is deposited bysputtering, as shown in FIG. 49, followed by further formation of aconductor film 6 d 1, which is made, for example, of copper or the likeby a plating method or CVD method. Thereafter, the conductor films 6 d1, 6 d 2 are polished by a CMP method to form a buried structure of thewiring 6 d in the second-layer wiring layer M2, as show in FIG. 50.After the CPM treatment, cleaning is carried out by use of the cleaningdevice 10 using the brush BR (FIG. 11). If an electric charge isaccumulated in the wiring 6 d of the wiring layers M1, M2 byelectrostatic action, the charge can escape through the insulating films7 b 1 to 7 b 4 to the ground potential GP, so that discharge is allowedat a stage where the charge accumulation in the wiring 6 d is low and itis possible to suppress the heat release value caused by the dischargeto a low level. Thus, a short-circuiting failure between the wirings 6d, 6 d of the wiring layers M1, M2 made mainly of copper as a mainwiring material can be suppressed or prevented. Thereafter, for the mainpurpose of suppressing and preventing copper from diffusing, the CMPsurface is subjected to plasma treatment in an atmosphere of ammonia orhydrogen gas, after which the insulating film 7 b 5 is deposited on themain surface of the wafer 1W so as to be in contact with the uppersurface of the wiring 6 d of the wiring layer M2. Thereafter, theinsulating film 7 b 5 is cleaned. In this case, the short-circuitingfailure of wirings ascribed to the discharge phenomenon between adjacentwirings can be suppressed or prevented in the same manner as set outhereinbefore.

Embodiment 7

In Embodiment 7, a modification in the case of application of theinvention to a Damascene wiring structure is considered. FIG. 51 is asectional view of an essential part at the same portion as region G ofFIG. 41 of a semiconductor device of Embodiment 7.

In Embodiment 7, a plurality of insulating films 7 e (7 e 1 to 7 e 10)are provided in the insulating portion 7 of a wiring structure. Theinsulating film 7 e in this embodiment has, aside from the function asan etching stopper, as set forth hereinbefore, the function ofsuppressing or preventing copper diffusion, and it is made, for example,of silicon nitride, silicon carbide, silicon carbide nitride or thelike, as mentioned hereinbefore. First, the insulating films 7 e 2, 7 e4, 7 e 6, 7 e 8, 7 e 10, respectively, are provided in contact with thewirings 6 c, 6 d of the respective wiring layers M0 to M4. This ensuresan improved capability of suppressing or preventing diffusion of copperin the wiring 6 d of the respective wiring layers M1 to M4. Theinsulating films 7 e 2, 7 e 4, 7 e 6, 7 e 8, 7 e 10 are provided thereonin contact with such insulating films 7 b 1, 7 b 3, 7 b 5, 7 b 7, 7 b 9for discharge, as shown in connection with Embodiment 1, and they aremade, for example, of a silicon-rich silicon oxide film or a siliconoxynitride (SiON) film. The insulating films 7 b 1, 7 b 3, 7 b 5, 7 b 7,7 b 9 are in contact with the plugs 6 b 2, 6 b 3 at the side surfacesthereof. On the other hand, the insulating films 7 e 3, 7 e 5, 7 e 7, 7e 9 are provided on the insulating films 7 a 3, 7 a 5, 7 a 7, 7 a 9,respectively. Moreover, the insulating films for discharge 7 b 2, 7 b 4,7 b 6, 7 b 8 are provided on and in contact with the insulating films 7e 3, 7 e 5, 7 e 7, 7 e 9, and they are formed of a silicon-rich siliconoxide film or a silicon oxynitride (SiON) film, respectively. Theinsulating films 7 b 2, 7 b 4, 7 b 6, 7 b 8 are in contact with the sidesurfaces of the wiring 6 d of the respective wiring layers M1 to M4. InEmbodiment 7, similar effects as those achieved in the foregoingEmbodiments 1, 2 can be obtained by the provision of the insulating film7 b. Likewise, in Embodiment 7, similar effects as attained inEmbodiment 3 can be obtained by selective provision of the insulatingfilm 7 b in the wiring layers M1 to M4 using copper as a main wiringmaterial, like the foregoing Embodiment 3. It will be noted that theelement layer and the wiring layer 5, respectively, are the same asthose of the foregoing Embodiment 6 and are not repeatedly explainedhere.

Next, an example of a method of manufacturing the semiconductor deviceaccording to Embodiment 7 will be described. FIG. 52 is a sectional viewof the wafer 1W obtained after completion of similar steps illustratedwith reference to FIGS. 43 to 46 in connection with Embodiment 6. Thematerial selected for an insulating film 15 b is the same as that used,for example, as the insulating film 7 e (7 e 2 to 7 e 5) and includes,for example, silicon nitride, silicon carbide, silicon carbide nitride,or the like. The through-hole TH at this stage passes through theinsulating films 7 b 4, 7 e 5 but is not fully opened. The bottom of thethrough-hole TH is stopped at an intermediate portion of the insulatingfilm 7 a 5 along the thickness direction thereof. Subsequently, theinsulating films 7 a 6, 7 a 5 are selectively etched under suchconditions that the insulating film 15 b is used as a mask and theinsulating films 7 e 4, 7 e 5 function as an etching stopper, therebyforming the wiring groove 13 and the through-hole TH, as shown in FIG.53. The through-hole TH of this stage is not fully opened as well, withits bottom being stopped at the insulating film 7 e 4. Thereafter, theinsulating films 15 b, 7 e 5, 7 e 4 are selectively etched to completethe wiring groove (an opening for wiring) 13 and the through-hole (anopening for wiring) TH. Part of the upper surface of the wiring 6 d ofthe wiring layer M1 is exposed from the bottom of the through-hole TH.Next, like the foregoing Embodiment 6, the wiring 6 d of a buriedstructure is formed in the wiring layer M2, as shown in FIG. 55. Then,as main purpose for suppressing and preventing copper from beingdiffused, after plasma treatment of the CMP surface in an atmosphere ofammonia or hydrogen gas, the insulating film 7 e 6 is deposited on themain surface of the wafer 1W by a CVD method, while being in contactwith the upper surface of the wiring layer M2, followed by furtherdeposition of the insulating film 7 b 5 by a CVD method.

In Embodiment 7, if an electric charge is accumulated such as in thewiring 6 d or the like during various processing procedures (including,for example, cleaning, plasma treatment and the like) in the course ofthe manufacture, the charge can escape from the side surfaces of theplug 6 d or the side surfaces of the plug 6 b connected thereto via theinsulating film 7 b to the ground potential, thereby permitting thecharge to be discharged at a stage of low accumulation in the wiring 6d. Thus, the heat release value caused by the discharge can besuppressed to a low level. This results in suppression or prevention ofthe short-circuiting failure between the wirings 6 d, 6 d, made ofcopper for a main wiring material, in the wiring layers M1, M2.

Embodiment 8

In Embodiment 8, an example of application of the invention to a measurefor static breakage will be considered. FIG. 56 is a plan view of theoverall arrangement of a semiconductor chip IV of a semiconductor deviceof Embodiment 8, FIG. 57 is an enlarged, plan view of region J in FIG.56, FIG. 58 is a sectional view, taken along line X2-X2 of FIG. 57, andFIG. 59 is a sectional view, taken along line Y1-Y1 of FIG. 57.

At the center of a square planar semiconductor chip IC, a square planarinternal circuit region CA1 is arranged (i.e. a non-hatched region atthe center of FIG. 5 and at the left upper portion of FIG. 57). Aplurality of processors, such as, for example, a DSP (digital signalprocessor) and the like, are arranged at the internal circuit region CA1and the respective processors are so arranged that parallel operationscan be performed, while sharing a diversity of processings at the sametime. To increase the processing power by carrying out paralleloperations of a multitude of instructions and data ensures a real time,high-speed operation of a desired processing, such as image processing.A peripheral circuit region CA2 is arranged from the outer periphery ofthe internal circuit region CA1 to the outer periphery of thesemiconductor chip 1C (i.e. a hatched region of FIGS. 56 and 57).

At the peripheral circuit region CA2, there are arranged a plurality ofinput and output circuit cells, a plurality of cells (externalterminals) PD and a guard ring GR provided therearound. The respectiveinput and output circuit cells have, for example, aside from an inputcircuit, an output circuit or an input and output bi-directionalcircuit, various interface circuits, such as a protection circuits forpreventing static breakage. The pads PD are arranged at given intervalsalong the outer periphery of the semiconductor chip 1C. The pads PDinclude pads for signals and pads for power supply. The pads PD forsignals are disposed in every input and output circuit cell. The pads Pdfor signals are electrically connected to the semiconductor regions 20for source and drain of a MISQ ESD forming a protection circuit forpreventing static breakage via the plug 6 b and the wiring 6 a of therespective wiring layers M1 to M4. The guard ring GR (GR1 to GR5) notonly serves to suppress or prevent impurities and moisture from enteringfrom the outside and also to terminate cracks of insulating filmsextending from the outer periphery, but also provides a path forpermitting an electric charge accumulated in the wiring 6 a inEmbodiment 8 to escape to the substrate 1S. The guard ring GR has thesame arrangement as the wiring 6 a, and it is formed as a frame in aplane along the outer periphery of the semiconductor chip 1C. Insection, the guard rings GR are formed in all the wiring layers M1 toM5, and they are mutually connected with one another through theconductor films 21 within the through-holes TH and also to the substrate1S via the conductor film 22 within the contact hole CH. Wirings 6 av 1to 6 av 4, 6 ag 1 t 6 ag 4 (6 a, 6) of the uppermost wiring layer M5 inthe peripheral circuit region CA2 indicate wirings for peripheralcircuit power supply, respectively. The wirings 6 av 1 to 6 av 3indicate a wiring for a high potential power supply voltage, forexample, of about 3.3 V, and the wiring 6 av 4 indicates a wiring for ahigh potential power supply voltage, for example, of about 1.2 V. Thewirings 6 ag 1 to 6 ag 4 indicate those wirings for a referencepotential power supply voltage, for example, of 0 (zero) V. The wirings6 av 1 to 6 av 4 and 6 ag 1 to 6 ag 4 (6 a, 6) are arranged in the formof a frame to surround the internal circuit region CA1 along the outerperiphery of the semiconductor chip 1C.

In Embodiment 8, the insulating film 7 b for discharge is patterned bylithography and dry etching so as to cover the peripheral circuit CA2alone, as is particularly shown as the hatched portion in FIGS. 56 and57. The insulating film 7 b is provided only in the uppermost wiringlayer M5, and it is deposited in contact with and covers a plurality ofwirings 6 a of the peripheral circuit region CA2 of the uppermost wiringlayer M5, a plurality of pads PD and the guard ring GR5. The provisionof the insulating film 7 b in this way permits a charge (staticelectricity) passing from outside of the semiconductor chip IC to agiven pad PD to be dispersed via the insulating film 7 b into other padsPD, the guard ring GR5 and the wirings 6 a and to escape to thesubstrate 1S. In this manner, the static breakage of the elements formedover the substrate 1S can be suppressed or prevented. Moreover, theprotection circuits for static breakage can be reduced in number andoccupation area. In addition, the protection circuit per se may not benecessary. Currently, because multistage protection circuits forpreventing static breakage are provided in every input and outputcircuit cell or the area of each protection circuit is increased, bothto obtain a satisfactory protecting effect, the chip size undesirablyincreases. According to Embodiment 8, however, the protection circuitarea can be reduced or eliminated, thus resulting in a reduction of thechip size. Using the semiconductor device of Embodiment 8, it becomesincreasingly possible to facilitate the miniaturization and portabilityof electronic instruments. The reason why the insulating film 7 b isprovided only at the uppermost wiring layer M5 is that the uppermostwiring layer M5 is the nearest portion where a charge passes fromoutside of the semiconductor chip 1C and is most effective foreliminating the charge. It should be noted that the invention is notlimited to this forming position of the insulating film 7 b, but manyalterations may be possible. For instance, the insulating film 7 b maybe provided, for example, in all the wiring layers M1 to M5,respectively, or it may be provided in more than two selected layers.The insulating film 7 b is provided at the peripheral circuit CA2 alone,for the reason that the elements of the internal circuit region CA1 donot suffer any static influence. In addition, the insulating film 7 bmay be patterned so as to cover the pad PD alone or the pad Pd and theguard ring GR alone in contact therewith.

FIG. 60 shows an example of a circuit arrangement of the peripheralcircuit region of the semiconductor device of Embodiment 8. The pad PDis electrically connected to the protection circuit ESD for staticbreakage protection and to an inverter circuit INV for input circuit.The protection circuit ESD is one which protects the internal circuitsfrom suffering from an overvoltage ascribed to static electricity, anddiode DESD and MISQ ESD are exemplified as such a protection circuitESD. The MISQ ESD in the is arranged to function similarly to adiode-connected diode. The inverter circuit INV has a pMISQpi and anMISQni, with its output being electrically connected to the internalcircuit. In Embodiment 8, the insulating film 7 b is arranged asdescribed above, so that when a high voltage (which is higher than theoperation voltage of the semiconductor device) is applied betweenadjacent pads PD owing to the static action, the adjacent pads PD areelectrically connected with each other through the insulating film 7 b.

FIG. 61 shows an example of a device layout of the input and outputcircuit cell I/O, and FIG. 62 is a plan view wherein wirings for aperipheral circuit power supply are added to the arrangement of FIG. 61.Reference numeral NWL in FIGS. 61 and 62 indicates an n-well, andreference numeral PWL indicates a p-well. The n-wells NWL and thep-wells PWL are arranged in the form of a frame along the peripheralcircuit power supply wirings. The input and output circuit cell I/Ocollectively has a series of circuits necessary for an interface forinternal circuits and the outside, such as an input and output buffer.The interface between the signal from the outside (e.g. 3.3 V) and aninternal signal (e.g. 1.2 V) is performed through the input and outputcircuit cell I/O. This requires the input and output circuit cell I/O tobe located in the vicinity of the pads PD. In addition, it is necessarythat at least two power supply voltages be supplied to the input andoutput circuit cell I/O. At the protection circuit region nearest to thepad PD, the protection circuit ESD is disposed. An output circuit isarranged at a subsequent-stage output buffer circuit region OBA, and aninput circuit, such as the above-mentioned inverter circuit INV or thelike, is arranged at an input buffer circuit region IBA, both beingoperated at a power supply voltage of about 3.3 V. A level shiftercircuit region LSA provided in a subsequent stage is one wherein acircuit for converting the voltage level of the input and output signalis arranged, and it is operated at power supply voltage of about 1.2 V.And, a PMIS constituting a circuit of each peripheral circuit region isarranged to the n-well NWL, and a nMIS is disposed at the p-well PWL.The power supply voltages applied to the respective circuits of theperipheral circuit region CA2 are supplied from the wirings 6 av 1 to 6av 4 and 6 ag 1 to 6 ag 4.

Although the invention has been particularly described based on variousexemplary embodiments, the invention should not be construed as limitedto these embodiments, and many alterations may be possible withoutdeparting from the spirit of the invention.

For instance, the method of forming the insulating film 7 b having sucha structure as set out in the foregoing Embodiment 2 may be carried outin the following way. For example, a plasma is formed in an atmospherecontaining a silane gas, for example, and the insulating film 7 a isexposed to the atmosphere of the plasma on the surface thereof to form asilicon-rich insulating film on the surface layer of the insulating film7 a. Alternatively, a plasma may be formed in an atmosphere containingnitrogen, followed by exposing the surface of the insulating film 7 a tothe plasma atmosphere to form a silicon oxynitride film on the surfacelayer of the insulating film.

Further, although a connection structure wherein bonding wires areconnected to the pads has been illustrated in connection with theforegoing Embodiments 1 to 8, the invention is not limited to thisstructure, but may be applied to a semiconductor device havingconnection structure wherein bump electrodes are connected to the pad.

Likewise, although the provision of the insulating film 7 b only at theperipheral circuit region in the foregoing Embodiment 8 has beenproposed, the insulating film 7 b may be provided, for example, in theinternal circuit region so as to permit an electric charge in thewirings in the course of manufacture to be discharged. In this case, theinsulating film 7 b of the peripheral circuit region and the insulatingfilm in the internal circuit region are separated even in the samelayer. This not only allows the charge in the wiring during the courseof manufacture of a semiconductor device to escape, but it also enablesone to disperse a charge generated by the static action at the outsideof a semiconductor chip. Because the insulating film 7 b is isolatedbetween the peripheral circuit region and the internal circuit region,an electric charge electrostatically generated at the outside of thesemiconductor chip can be prevented from transmitting through theinsulating film 7 b.

Although applications to semiconductor devices having a MIS or a logiccircuit, which are in the field of utility serving as the background ofthe invention made by us, have been considered, the invention should notbe construed as limited thereto. For instance, the invention isapplicable to semiconductor devices having memory circuits, such as, forexample, a DRAM (dynamic random access memory), a SRAM (static randomaccess memory), a flash memory (EEPROM: electrically erasableprogrammable read only memory) and the like, or to consolidatedsemiconductor devices wherein such a memory circuit as indicated aboveand a logic circuit are disposed on the same substrate. Alternatively,the invention may be applied to a semiconductor device having a bipolartransistor.

The effects obtained by a typical embodiment according to the inventionis briefly described below.

When an insulating film having high conductivity is formed between awiring that is electrically connected to a semiconductor substrate and afloating wiring, the charge accumulated in the floating wiring in thecourse of manufacture of a semiconductor device is allowed to bedischarged to the electrically connected wiring. Thus, theshort-circuiting failure between the wirings can be suppressed orprevented from occurring.

The effects obtained by a typical embodiment according to the inventionis briefly described below.

Because an insulating film in a wiring structure of the semiconductordevice has a function of permitting an electric charge accumulated inthe wiring to escape, the short-circuiting failure ascribed to thedischarge of the charge in the wiring can be suppressed or preventedfrom occurring.

1. A semiconductor integrated circuit device comprising: a semiconductorsubstrate having a main surface such that a peripheral region of themain surface surrounds a circuit region of the main surface; a firstinsulating film formed over the main surface; external terminals formedover the first insulating film; a guard ring formed over the firstinsulating film, the guard ring being comprised of a same metal wiringlayer as that of the external terminals and provided around the externalterminals; and second insulating films formed over the first insulatingfilm and over the guard ring and contacting the external terminals,wherein the second insulating films of the circuit region and the secondinsulating films of the peripheral region are formed separately and areisolated from each other.
 2. A semiconductor integrated circuit deviceaccording to claim 1, wherein the second insulating films are comprisedof a material including silicon and nitrogen, respectively.
 3. Asemiconductor integrated circuit device according to claim 1, whereinthe second insulating films are comprised of a silicon-rich insulatingfilm, respectively.
 4. A semiconductor integrated circuit deviceaccording to claim 1, wherein the second insulating films are comprisedof a silicon oxynitride insulating film, respectively.
 5. Asemiconductor integrated circuit device according to claim 1, whereinguard rings are formed in each of plural wiring layers and arecontacting with each other through contact holes.
 6. A semiconductorintegrated circuit device comprising: a semiconductor substrate having amain surface such that a peripheral region of the main surface surroundsan internal circuit region of the main surface; a first insulating filmformed over the main surface; external terminals dispersed over theperipheral region at a regular interval, surrounding the internalcircuit region and formed over the first insulating film; a guard ringprovided radially further away from the internal circuit region than arethe external terminals and formed over the first insulating film;wherein the guard ring is comprised of a same metal wiring layer as thatof the external terminals; and second insulating films formed in theinternal circuit region and the peripheral region, respectively, whereinthe second insulating film of the peripheral region is formed over thefirst insulating film and over the guard ring and is contacting theexternal terminals, and wherein the second insulating films of thecircuit region and the second insulating films of the peripheral regionare formed separately and are isolated from each other.
 7. Asemiconductor integrated circuit device according to claim 6, furthercomprising a multi-level wiring arrangement on the main surface of thesemiconductor substrate, wherein a separate second insulating film isformed over the wirings corresponding to each wiring level, verticallyabove the internal circuit region, and over the first insulating film ofeach underlying inter-level insulating layer, respectively.
 8. Asemiconductor integrated circuit device according to claim 7, whereinlike-positioned guard ring units are formed in through holes at each ofmulti-level wirings in the peripheral region so that together they forma stacked arrangement of contacting conductive layers in which theoutermost conductive layer thereof is covered by the second insulatingfilm of the peripheral circuit, which second insulating film alsocontacts the external terminals, and in which the innermost conductivelayer of the stacked arrangement is in electrical contact with thesemiconductor substrate.
 9. A semiconductor integrated circuit deviceaccording to claim 8, wherein the external terminals are bonding pads orpads for solder connection and are arranged in a ring-like manner overthe outermost wiring layer of the semiconductor integrated circuitdevice, and wherein the guard ring forms an annular ring-like shapesurrounding the ring-like arrangement of the bonding pads, in a verticalview above the main surface.
 10. A semiconductor integrated circuitdevice according to claim 9, wherein the second insulating films arecomprised of a material including silicon and nitrogen, respectively.11. A semiconductor integrated circuit device according to claim 9,wherein the second insulating films are comprised of a silicon-richinsulating film, respectively.
 12. A semiconductor integrated circuitdevice according to claim 9, wherein the second insulating films arecomprised of a silicon oxynitride insulating film, respectively.
 13. Asemiconductor integrated circuit device according to claim 9, wherein asilicon content of the second insulating film is higher than that of thefirst insulating film.
 14. A semiconductor integrated circuit deviceaccording to claim 7, wherein the external terminals are bonding pads orpads for solder connection and are arranged in a ring-like manner overthe outermost wiring layer of the semiconductor integrated circuitdevice, and wherein the guard ring forms an annular ring-like shapesurrounding the ring-like arrangement of the bonding pads, in a verticalview above the main surface.
 15. A semiconductor integrated circuitdevice according to claim 6, wherein like-positioned guard ring unitsare formed in through holes at each of multi-level wirings in theperipheral region so that together they form a stacked arrangement ofcontacting conductive layers in which the outermost conductive layerthereof is covered by the second insulating film of the peripheralcircuit, which second insulating film also contacts the externalterminals, and in which the innermost conductive layer of the stackedarrangement is in electrical contact with the semiconductor substrate.16. A semiconductor integrated circuit device according to claim 6,wherein the external terminals are bonding pads or pads for solderconnection and are arranged in a ring-like manner over the outermostwiring layer of the semiconductor integrated circuit device, and whereinthe guard ring forms an annular ring-like shape surrounding thering-like arrangement of the bonding pads, in a vertical view above themain surface.
 17. A semiconductor integrated circuit device according toclaim 15, wherein a silicon content of the second insulating film ishigher than that of the first insulating film.
 18. A semiconductorintegrated circuit device according to claim 7, wherein a siliconcontent of the second insulating film is higher than that of the firstinsulating film.
 19. A semiconductor integrated circuit device accordingto claim 1, wherein a silicon content of the second insulating film ishigher than that of the first insulating film.
 20. A semiconductorintegrated circuit device according to claim 5, wherein a siliconcontent of the second insulating film is higher than that of the firstinsulating film.